Lateral power devices typically operate with a voltage in the range 20 V to 1.2 KV. Power devices typically operate with a current in the range 10 mA to 50 A and typically higher than 0.1 A and smaller than 5 A. Such devices may also be referred to as “high voltage/power devices”. These devices are typically capable of delivering from a few milliwatts to 1 Watt or even a few tens of Watts of power. Their applications range from domestic appliances, electric cars, motor control, and power supplies to RF and microwave circuits and telecommunication systems.
Lateral power devices have the high voltage/low voltage main terminals (variously called the anode/cathode, drain/source and emitter/collector) and the control terminal (termed the gate or base) placed at the top surface of the device in order to be easily accessible. In power ICs, such devices are often monolithically integrated with CMOS-type or BiCMOS-type low voltage and/or low power circuits and therefore it is desirable that the lateral high voltage devices are CMOS compatible. It is also possible that several high voltage, power devices may be integrated within the same chip: One or more silicon dice comprising one or more power devices may be housed in the same package as one or more silicon dice comprising low voltage, low power circuits. This co-packaged arrangement may benefit from the use of lateral power devices since the power die or dice and low voltage die or dice may be mounted on the same conductive die attach or lead frame, which may be connected to a reference potential such as ground or earth.
There are two main technologies that have emerged in the high voltage/power integrated circuit field. The first, Junction-Isolated (JI) technology, is based on using reverse-biased junctions for isolating adjacent devices. The second is using a buried insulating material such as silicon dioxide as a way to isolate the silicon active layer from the silicon substrate. Alternative technologies such as out PowerBrane technology (see U.S. Pat. No. 6,703,684; U.S. Pat. No. 6,900,518; and U.S. Pat. No. 6,927,102), where a membrane is used for isolation. In the first technology, Junction-Isolation, the high voltage device incorporates a high voltage RESURF (Reduced SURface Field effect) type junction. The RESURF effect is based on a more extensive growth of the depletion region at the surface than what is predicted through applying the 1D Poisson theory. This is achieved by the existence of two junctions adjacent to the drift region (one lateral and one vertical) that interact to create a more extensive depletion region inside the drift region. The semiconductor substrate has p-type conductivity and is ideally more lowly doped than the n-type drift region. In this case a depletion region forms deep into the semiconductor substrate (or a virtual substrate) as well as vertically in the drift region, resulting in a more extensive growth of the depletion region than that predicted by 1D junction. This allows the doping charge to be set at a higher value than that predicted by the one-dimensional Poisson theory, thereby lowering the on-state resistance of the device. In the second technology, SOI technology, part of the potential drop during the blocking mode can be supported across the buried insulating material. The substrate underneath is grounded and acts in a similar way to a field plate, which helps to expand the depletion region in the drift region more substantially than that predicted by the 1D junction Poisson theory.
To further reduce the resistance of the drift region, by increasing its doping and reducing (slightly) its length a double RESURF layer can be added. This layer is referred to as the p-top layer in this specification. The p-top layer can also be used to enable a single RESURF effect in SOI and membrane power devices. The p-top layer forms a third junction with the drift region, just below the surface. This junction is parallel to that formed between the n-drift and p-substrate layers. The action of this junction is similar to that of the RESURF effect and for this reason this approach is referred to as a double RESURF approach. In theory double RESURF can almost double the charge in the n-drift doping as compared to single RESURF. In some double RESURF implementations a further layer above the p-top layer may also be provided.
The p-top layer is commonly placed under the field oxide. Its presence can also help to reduce the hot carrier injection effect as it pushes the flow of the current in the bulk away from the silicon/oxide interface and reduces the electric field component that is perpendicular to the oxide/silicon interface.
The p-top layer may be used both in LDMOSFETs and LIGBTs as well as other lateral power devices that use the double RESURF effect. The MOS channel is usually built in the p-well of a lateral power device. It is often that the p-well is present in the CMOS process and is a deep diffusion (more than 3 μm and more commonly over 5 μm). The p-well diffuses both vertically and laterally. For a junction depth of 5 μm, a lateral diffusion length of approximately 4 μm is expected. When the transistor is biased in the on-state, the p-well/n-drift region is reverse biased and therefore a depletion region is formed around the physical junction extending laterally in the n-drift region. This depletion region, in combination with the depletion region formed around the p-top in the n-drift layer, tends to obstruct the electron flow (spreading) from the channel/accumulation layer into the drift region. This is similar to an unwanted (parasitic) JFET effect. The parasitic JFET effect introduces an additional voltage drop in the on-state and hence higher on-state losses. Moreover, since the p-well and the p-top are done at different stages in the process sequence, using different masks, there could be slight misalignment (within certain process tolerances, e.g. +/−0.5 μm) between these two layers. This misalignment results, however, in a smaller or larger pitch between the two depletion layers and, as a result, a smaller or larger parasitic voltage drop. This parasitic voltage drop is increasing with the voltage applied to the high voltage terminal (the high voltage terminal of a power device is often referred to as the drain, anode or collector terminal). The parasitic JFET effect leads therefore to non-uniform on-state behaviour from wafer to wafer and/or lot to lot.